Normal EDA
Accelerate verification for the most complex chip designs. Scale custom silicon.
The chip industry is facing the silicon complexity crisis – more complexity in chips exacerbates the amount of time required to go to market.
Humans and LLMs are struggling to tame the mathematical complexity of design logic. Verification remains manual and fragmented.
Normal EDA is the unified AI verification stack changing that.
Humans and LLMs are struggling to tame the mathematical complexity of design logic. Verification remains manual and fragmented.
Normal EDA is the unified AI verification stack changing that.
What is Normal EDA?
Normal EDA is a holistic stack for complex IP and SoC verification. Teams use Normal EDA to generate full, production-grade collateral from specs; accelerating signoff, reducing engineering effort, and surfacing edge cases that humans and general purpose LLMs miss.
Test plan generation
Normal EDA takes any design spec and automatically generates thousands of tests with the goal of reaching 100% functional coverage. Normal EDA can be integrated with your existing tooling workflows and iterates with your verification engineers based on human feedback.
Testbench code generation
Normal EDA generates System Verilog/UVM code that can be integrated into the user’s existing testbench code. As Normal EDA generates code, users can view Normal EDA's sequence of actions, interject in real-time, and offer feedback.
Human-in-the-loop
Normal EDA augments verification engineers by offering a human-in-the-loop feedback system, in which engineers review results, identify overlooked edge cases, and guide improvements.
Traceability
Normal EDA intelligently cites your tests to multiple references in the spec. Unlike legacy verification environments, Normal EDA dynamically links tests to an exact quote, table, diagram, etc., without requiring the user’s manual effort. For each revision of the design, Normal EDA auto-updates all verification collateral and associated links to the spec, ensuring humans can understand at a glance how collateral has changed.
Technology
Powered by autoformalization. Normal EDA is backed by foundational “auto-formalizing AI,” which autonomously builds a mathematical model from specs into a logically consistent ontology powering industry-leading functional verification.
Frequently asked questions
1. What are the prerequisites on what the inputs should be?
Normal EDA is trained end-to-end on specifications and complete verification collateral, and post-trained similarly on available customer data.
Normal EDA takes design specifications as input, ranging from high-level architectural documents to more detailed micro-architecture descriptions.
Within the design spec, Normal EDA processes a wide range of elements, including textual descriptions, truth tables, timing diagrams, and command sequences. The formal model constructs an internal representation of flow and timing from this input.
Normal EDA does not explicitly issue “incompleteness” warnings, but it can identify missing or unclear sections in product specs. It handles this ambiguity by inferring likely behaviors and corresponding tests; moreover, Normal EDA is complemented by our human-in-the-loop feedback system, in which engineers further refine the specification or approve inferred tests.
In the future, as Normal EDA evolves to handle more complex workflows from verification engineers, we expect it to handle incomplete specs, revisions, and multiple specs at once.
2. How does Normal EDA achieve “logical understanding” of non-textual design specs?
Normal EDA uses multimodal AI to interpret graphical inputs - such as timing diagrams and waveform images - and automatically derives the corresponding stimulus and checks. By pulling coverage criteria directly from these visual sources, Normal EDA ensures comprehensive verification without relying solely on text-based descriptions.
3. What is in the test plan?
The test plan is presented as a structured document, split into individual test items created from directed tests and crosses of different features. For each test item, Normal EDA describes what will be tested (relevant command sequences, expected values, etc.), links to the source in the spec, and enumerates a list of test cases. In addition, the test plan can be exported as a .csv.
4. How do you ensure the quality of the output?
We use a combination of human expertise and AI assessment. Verification engineers initially review a sample of the generated collateral to establish a grading standard. These judgments train an AI-based quality scoring system that we apply to the rest of the outputs. We continuously incorporate feedback from customers, especially those in regulated industries - to refine our quality assurance processes.
5. What security certifications do you have in place?
We currently prioritize SOC 2 compliance. If your company requires other specific certifications or compliance guarantees, we are open to accommodating where possible. Security and data protection are top priorities for us, and we will collaborate with you to meet your standards.
6. Do you output testbench code?
Yes, stimulus code is a beta feature. In the future, we will expand our capabilities to generate UVM-compatible testbench code and link it to the test plan.
7. Do you integrate with verification tooling like XCelium?
Yes, we integrate with existing verification simulation environments such as VCS and XCelium and rely on these tools to run simulations and update coverage for Normal EDA’s generated tests.