Home

Accelerate verification for the most complex chip designs. Scale custom silicon.

NORMAL EDA

AI-accelerated co-design for silicon engineering teams.

Structured representations of the chip

The Ontology grounds downstream collateral generation in a source of truth.

Intelligent Verification Planning

Normal EDA structures its understanding of specification documents into a hierarchical test plan with traceability between source docs and tests.

Generate Stimulus

Convert the test cases into System Verilog stimulus, run simulations, and track coverage within Normal CLI.

Normal EDA builds an understanding of your design intent and uses it to generate, verify, and optimize engineering artifacts — learning continuously from your team's feedback.

NORMAL ASICs

Normal’s physics-based ASICs relax the assumptions made in traditional computing, allowing for stochastic, stateful, and asynchronous computing, unlocking orders-of-magnitude more efficient compute.

As Normal EDA makes the chip design process look more like software, Normal ASICs explores what that new paradigm makes possible - applying AI to silicon and silicon to AI to enable ultra efficient ASICs for every workload.

THE CO-DESIGN ERA

We envision a world where software and silicon share the same physics, fundamentally changing how hardware is built.

Hardware

applications

We believe that ASICs of the future will converge with physics. Cutting-edge GenAI models already look like dynamical equations of physical systems. The most effective hardware will be built to reflect those same principles.

The semiconductor industry’s leading companies use Normal EDA to scale new hardware and enable 2x faster time-to-market

Writing

Insights & breakthroughs, shaping the future of computing.

4.23.2026

Manual translation of chip standards into verification artifacts is a major bottleneck in chip design. DRAMBench, developed by Normal Computing and Fraunhofer IESE, benchmarks AI systems that turn natural language DRAM specifications into timed Petri net models.

From Specifications to Formal Models: Autoformalizing Memory Chips with DRAMBench

3.25.2026

Fortune Exclusive: Normal Computing raises $50M from Samsung Catalyst to tackle soaring AI chip costs and power demands

3.25.2026

Normal Computing Raises $50M Led By Samsung Catalyst to Accelerate Silicon Design and Solve AI Hardware Energy Crisis

3.2.2026

How one Normal engineer used AI agents to build a practical verification toolchain on top of CIRCT: simulation, formal verification, mutation testing, and more.

Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days

1.12.2026

A Complete Decomposition of Stochastic Differential Equations